Low k dielectric etch in high density plasma etcher

ABSTRACT

An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C 4 F 8  and C 2 F 6  etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.

[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 08/864,868 filed May 12, 1997.

FIELD OF THE INVENTION

[0002] This invention relates to processes for integrated circuit manufacturing, and in particular to processes for plasma etching of low dielectric constant dielectric layers and wafers made by the process.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits are becoming ever smaller, faster, and cheaper to produce. Accordingly, device geometries and minimum feature sizes are shrinking, and are currently commercially available down to 0.25 microns. In this size regime, the resistance and capacitance of interconnect lines providing electrical connection between devices plays an increasingly large role in determining speed and performance of the integrated circuit. As a result, in integrated circuit research and development, increasing attention has focused on reducing the resistance and capacitance of interconnect lines.

[0004] The distributed capacitance of a metal line running over or through a dielectric layer is proportional to the dielectric constant of the dielectric. Therefore, utilizing dielectrics having a low dielectric constant in integrated circuit processes, as the interlevel dielectric in multilevel metallization structures by way of example, is one important method of increasing speed and improving performance. One such dielectric with a low dielectric constant is a spin-on material known as HSQ, Hydrogen Silsesquioxane, which is utilized as a planarizing bottom layer in an interlevel dielectric stack, as illustrated in FIG. 1a. In this capacity, a contact or via etch must be performed through the HSQ and any other dielectric layers in the stack to provide an aperture for depositing a low resistance connection between metal layers. This contact or via etch process must be highly anisotropic in order to etch deep but narrow vias or contacts i.e., high aspect ratio vias or contacts. It must also have excellent selectivity with respect to the stopping material, which for most current applications is Ti or TiN, but may be Si, silicon nitride, or metals such as Al, Cu, or Ta, depending on the details of the process. Selectivity is required in order to allow overetch, so that the deepest contact/via is etched through without destroying the region beneath the shallowest contact/via. If the wafer surface is not exactly planar, there will always be contacts/vias of somewhat differing depths.

[0005] Standard contact/via etch processes have been developed having the requisite selectivity and anisotropy for interlevel dielectrics comprising oxides such as TEOS (tetraethylorthosilicate). One known contact/via dry etch method is performed in a high density plasma (HDP). Specialized etch machines have been developed for HDP etch such as the Applied Materials Centura 5300 or the Lam 9100. These high ion density machines operate in a lower pressure regime than standard plasma etch machines. The lowered pressures result in a more anisotropic etch, due to decreased ion collisions and scattering. The generally used etch gas for oxide etch comprises C2F6. The process selectivity of oxide to an underlying etch stop layer is generally achieved by allowing the formation of polymer, which is deposited in the contact/via during oxide etch but reacts away faster than it deposits. When the underlying layer is reached, the polymer deposits on the surface of non-oxygen containing layer faster than it volatilizes and causes etch stop.

[0006] However, when HSQ has been previously etched using C2F6 chemistry in an HDP reactor for a large wafer, however, etching would stop in some vias before reaching the etch stop layer and this would prevent effective HSQ etch, particularly when the HSQ layer is below a TEOS layer. Additionally, substantial etch non-uniformity has occurred from the center to the edge of the wafer. This has resulted in problems with “punch-through” of the etch stop layer, i.e., etching completely through the etch stop, on portions of the wafer. One factor believed to contribute to these effects is that the HSQ contains hydrogen and contains less oxygen than silicon dioxide. This is believed to promote increased polymer formation and deposition during HSQ etch as compared to SiO2 etch. Attempts by several research groups to solve these problems and thereby realize a useful TEOS/HSQ etch in an HDP reactor have until now been largely unsuccessful.

SUMMARY OF THE INVENTION

[0007] It is therefore an object of this invention to provide an improved wafer for integrated circuits and a manufacturing process in a high-density plasma reactor which can be utilized to etch high aspect ratio contacts or vias through dielectrics where the dielectric includes HSQ.

[0008] Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which does not evidence an etch-stop effect at a dielectric interface during HSQ etch.

[0009] Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which has high anisotropy.

[0010] Another object of this invention is to provide a manufacturing process for etching HSQ in a high-density plasma reactor which has high selectivity over underlying layers.

[0011] Another object of this invention is to provide a wafer and a manufacturing process therefor for etching HSQ in a high-density plasma reactor which has improved across-the-wafer uniformity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1a shows a cross section of a multi-level metallization structure before contact/via etch, showing use of a low K spin-on layer in a dielectric stack.

[0013]FIG. 1b shows the structure of FIG. 1a after contact/via etch.

[0014]FIG. 2 shows the molecular structure of HSQ.

[0015]FIG. 3 shows a schematic diagram of a high-density plasma etch reactor.

[0016]FIG. 4a is a proportional schematic of an actual SEM photograph of HSQ layer etched by the standard C2F6 contact/via etch process in the wafer edge region of an 8 inch wafer.

[0017]FIG. 4b is a proportional schematic of an actual SEM photograph of HSQ layer etched by the standard C2F6 contact/via etch process in the wafer center region of an 8 inch wafer.

[0018]FIG. 5a is a proportional schematic of an actual SEM photograph of the best mode HSQ etch of vias in the wafer edge region of an 8 inch wafer.

[0019]FIG. 5b is a proportional schematic of an actual SEM photograph of the best mode HSQ etch of vias in the wafer center region of an 8 inch wafer.

[0020]FIG. 6a is a proportional schematic of an actual SEM photograph of the best mode HSQ etch after tungsten via fill in the wafer edge region of an 8 inch wafer.

[0021]FIG. 6b is a proportional schematic of an actual SEM photograph of the best mode HSQ etch after tungsten via fill in the wafer center region of an 8 inch wafer.

[0022]FIG. 7a is a proportional schematic of an actual SEM photograph of a non-optimized HSQ etch, showing no etch stop at the 8-inch wafer edge.

[0023]FIG. 7b is a proportional schematic of an actual SEM photograph of the HSQ etch of FIG. 7a, but showing etch stop at the wafer center.

DETAILED DESCRIPTION OF THE INVENTION

[0024]FIGS. 1a and 1 b illustrate the use of a low-K spin-on dielectric such as HSQ in a multi-level metallization structure on silicon wafer 1 with patterned active regions therein. FIG. 1a shows the structure before contact/via etch. First layer metal lines 2 with critical dimension of approx. 0.35 microns or less are electrically isolated from one another, and from the next layer of metal, by a dielectric layer 4. Dielectric layer 4 which may be approx. 0.5 to 2 microns in thickness is comprised of a spin-on layer 6, HSQ by way of example, and by deposited oxide layer 8, PETEOS (Plasma Enhanced TEOS) by way of example. In general, when HSQ is used it needs a cap layer such as TEOS above it since HSQ is hydrophilic. Via openings 10 are patterned into resist layer 12. FIG. 1b shows the structure after contact/via etch is performed. High-aspect ratio vias 14 require high anisotropy of the etch. Typical via dimensions are approx. 0.25-0.4 micron diameter, with depths ranging from 0.5 to 2.0 microns, depending on the range of dielectric layer thickness across wafer 1. Etch stop layer 16 is generally an anti-reflective coating (ARC) such as Ti or TiN, but it may be a metal such as Al, Al alloy, Cu, Ta, or it may be silicon or silicon nitride. Good etch selectivity for dielectric over all of these materials is important to achieving a broadly applicable HSQ etch, because of the differing via depths. In the best mode, a TiN ARC layer 56, FIG. 5a, with thickness of approximately 1100 A is used as the etch stop. The required etch selectivity of dielectric over the etch stop is calculated by the amount of overetch required and the thickness of the etch stop layer. In this case, since via depths range between 0.5 and 2.0 microns across the wafer, the shallowest, i.e. 0.5 micron vias will be etched down to the etch stop layer when 1.5 microns of dielectric remains to be etched for the deepest, i.e., 2.0 micron vias. (The assumption is made here that the etch rates of all the dielectrics in the stack are substantially equal). Accordingly, at least a portion of the TiN etch stop layer must remain across the entire wafer after overetch of 1.5 microns of dielectric in order to function as an effective etch stop. In order to have at least 100 Angstroms (i.e., 0.01 microns) of TiN remaining of the 1100 thick TiN ARC etch stop layer following overetch of 1.5 microns dielectric, the selectivity of HSQ and the remaining dielectric layer over TiN must be a minimum of 15:1.

[0025] After contact/via etch, second level metal 17 is deposited into the vias 14 to form electrical interconnection to the next metal layer.

[0026]FIG. 2 illustrates the molecular structure of HSQ. The particular HSQ material used for the inventive process development is sold by Dow Corning under the trade name Flowable Oxide (FOx). Its chemical composition is (HSiO3/2)n.

[0027]FIG. 3 is a schematic diagram of the Applied Materials Centura 5300 HDP etch reactor, which was used to develop the inventive process. Wafer 18 is mounted in etch reactor 20 on electrostatic chuck 22. RF power supply 24 provides wafer bias. High density plasma 26 is generated by source inductive RF power supply 28. Walls 30 are temperature controlled by heated antenna assembly 32. Roof 34 is temperature controlled by top heater 36 having a hot fluid (ethylene glycol) pumped therethrough. Wafer temperature is controlled by backside cooler or chiller 38, with He flow between cooled chuck 22 and wafer 18. Reactor gases are introduced into the reactor via gas inlets 40. Vacuum pump 42 controls reactor pressure.

[0028] The HDP machine operates at an elevated plasma ion density (approx. 1012 cm−3) in the 1-5 milliTorr pressure range while maintaining a high etch rate. Etch anisotropy is improved over other types of plasma reactors. An additional feature of the HDP machine is the capability of controlling temperatures of roof 34 and wall 30, and thereby modifying polymer deposition on wafer 18. For a standard prior art contact/via etch of TEOS using C2F6 etch chemistry, walls 30 and roof 34 are maintained at a high temperature (approx. 290 C.) while wafer 18 is cooled by chiller 38 at approx. −10 to +10 C. Most of the polymer formed is therefore deposited on the relatively cool wafer. The polymer formation is a critical factor in providing a high selectivity of the dielectric etch rate over the etch rate of the etch stop layer. During dielectric etch, oxygen from the SiO2 reacts with carbon from the C2F6 etch gas, and polymer formed and deposited at the exposed SiO2 areas is volatilized. When the non-oxygen containing stopping layer, Ti or TiN by way of example, is reached, polymer deposition occurs and “back-fills” the etched region, causing etch stop.

[0029] Polymer deposition is not uniform across the wafer. The wafer center 44, being farthest from the radiant heat source of walls 30, has the coolest temperature and thereby the greatest amount of polymer deposition. This effect is illustrated in Table 1, showing resist loss across a wafer during prior art standard contact/via etch. TABLE 1 Resist loss uniformity using standard contact/via etch. Position on Wafer Resist loss (Angstroms) Left edge 5866 Center 1664 Right edge 5390

[0030] Resist loss during etch is inversely proportional to the amount of polymer deposited, so the Table qualitatively demonstrates the increased polymer deposition at the wafer center. This level of non-uniformity of polymer does not adversely affect the standard TEOS etch, since due to the high oxygen content of the TEOS, a wide process window of polymer deposition amount still results in effective TEOS etch. However, when etching HSQ, the hydrogen reacts with the fluorine in the etch gas, releasing additional free carbon and resulting in greater polymer formation at the HSQ regions, which causes the etch to stop before completely etching through the HSQ, particularly at the wafer center 44. Since HSQ is less effective than SiO2 at preventing and reacting with deposited polymer, there is a smaller process window of polymer amount which will prevent etch-stop during the HSQ etch and still maintain the etch stop at the underlying layer. Prior art attempts to etch HSQ have not succeeded in placing both the wafer center 44 and the wafer edge 46 within this process window due to the degree of polymer deposition non-uniformity, particularly when the dielectric structure comprises a layer of HSQ under a layer of TEOS. FIG. 4 shows HSQ etch using the aforementioned prior art standard contact/via etch with C2F6 chemistry, and showing etch stop of the HSQ at the wafer edge 46 (FIG. 4a) and wafer center 44 (FIG. 4b).

[0031] It was experimentally determined that the polymer deposition and etch-stop during HSQ etch is pronounced at the interface between the HSQ and an overlayer of TEOS. The etch stop enhancement is also seen near the HSQ/underlying TiN layer interface. A likely explanation is that there exists a non-uniform hydrogen concentration in the HSQ, with hydrogen enrichment near the top and bottom of the HSQ layer.

[0032] The inventive process improves via etch uniformity across the wafer. This process provides a wafer having both edge and center vias falling within the process window yielding vias with acceptable profile and etch stop characteristics. The improved process lowered the roof temperature from approx. 290 C. to approx. 220-230 C. and lowered the wall temperature to approx. 200 C. Since the radiant heat source near the wafer edges is now cooler, the temperature variation across the wafer is decreased and therefore the uniformity of the polymer deposition rate improves. However, the lowered roof and wall temperatures also resulted in lower total polymer deposition on the wafer, which is compensated for in the inventive process by providing additional C4F8 to the etch gas. The carbon-rich C4F8 provides enhanced polymer formation which is necessary to avoid punch-through of the Ti or TiN during overetch. With the improved uniformity of polymer deposition, both the wafer edge and center fall within the acceptable process window when the C4F8 pressure is properly adjusted. The improved uniformity of polymer deposition with the lower roof and wall temperature and using C2F6/C4F8 mixture is illustrated in Table 2. Table 2 shows resist loss during contact/via etch for the inventive process compared with the standard contact/via etch process as shown in Table 1. TABLE 2 Resist Loss Uniformity using standard vs inventive contact/via etch Resist Loss in Angstroms (standard Position on wafer etch/inventive etch) Left edge 5866/3571 Center 1664/1418 Right edge 5320/2737

[0033] Other chemical methods of enhancing polymer formation, such as addition of CH3F to the etch gases, have not been successful. This is thought to be due to difficulties in process control resulting from excess hydrogen in the etch gas.

[0034] The best mode etch process in the Applied Materials Centura 5300 HDP reactor comprises:

[0035] 8 sccm C4F8

[0036] 5 sccm C2F6

[0037] 95 sccm Ar

[0038] 2000 W Source power

[0039] 1500 W Bias power

[0040] 4 mTorr pressure, with throttle valve to vacuum pump open 100%

[0041] 230 C. roof temperature

[0042] 200 C. wall temperature

[0043] −10 C. chiller

[0044] 15 Torr He (coolant between wafer and chuck)

[0045]FIGS. 5a and 5 b show etched vias at wafer edge 46 (FIG. 5a) and wafer center 44 (FIG. 5b), using the best mode etch process, for a 0.25 micron metallization technology, wherein the via diameter is approximately 0.35-0.4 micron. Both TEOS layer 52 and HSQ layer 50 are completely etched, and TiN layer 56 provides an effective etch stop. The slight bowing of the via walls 58 seen in the HSQ layer has been determined to be an artifact of the SEM process, due to the physical characteristics of the spin-on HSQ. FIGS. 6a and 6 b show similarly etched vias after tungsten via fill at the edge 46 (FIG. 6a) and center 44 (FIG. 6b), and the bowing is no longer seen. It is concluded that the bowing occurs when the etched wafer without filled vias is cleaved for the SEM photograph.

[0046] Marginally acceptable across-the wafer etch uniformity has been achieved with process parameters comprising:

[0047] 10 sccm C4F8

[0048] 5 sccm C2F6

[0049] 95 sccm Ar

[0050] 2200 W Source power

[0051] 1500 W bias power

[0052] 10 mTorr pressure

[0053] 230 C. roof temperature

[0054] 215 C. wall temperature

[0055] −10 C. chiller

[0056] 15 Torr He

[0057] Under these process conditions, slight evidence of the beginnings of HSQ etch stop at the wafer center 44 is observed, as shown in FIG. 7b, although no etch stop is seen at wafer edge 46, as shown in FIG. 7a.

[0058] Comparison with the best mode process parameters suggests quite narrow acceptable parameter ranges of:

[0059] 5-10 sccm C4F8

[0060] 5-9 sccm C2F6

[0061] 50-200 sccm Ar

[0062] 1800-2200 W Source power

[0063] 1300-1700 W bias power

[0064] 1-15 mTorr pressure

[0065] 200-240 C. roof temperature

[0066] 200-220 C. wall temperature

[0067] −20-0 C. chiller

[0068] 10-15 TorrHe

[0069] Although selectivity of HSQ to underlying non-oxygen containing layers such as nitride or metal will vary slightly from the selectivity to Ti or TiN, due to the variation of the underlying layer etch rate by the C4F8/C2F6 etch gas during the brief period before polymer backfill shuts down the etch, the mechanism is expected to be similar for the various underlayers. Slight tuning of etch parameters might be needed to optimize selectivity.

[0070] By utilizing the inventive process for etching the low-K dielectric HSQ in an HDP reactor, contacts/vias with high aspect ratio and geometries of 0.35-0.4 microns and below can be effectively etched, across the entire 8 inch wafer diameter, through the low-dielectric constant dielectric material to the etch stop layer, and metal line capacitances can be reduced, improving ultimate device frequency. The inventive etch process can also be employed for other applications of the HSQ in the process, such as the Damascene process.

[0071] Whereas the process as described above utilizes the Applied Materials Centura 5300 etch system to etch HSQ over Ti or TiN layers, it is not limited to these exact embodiments. Other similarly designed HDP reactors such as the Lam 9100 may be utilized with minimal process parameter tuning. Other non-oxygen containing etch stop underlayers may be used, again with minimal process parameter tuning. Additionally, other dielectrics with similar chemical composition to HSQ such as Spin-On Glass (SOG) are expected to behave similarly. The inventive process is effectively utilized to etch silicon dioxide materials such as TEOS, as well as other dielectrics comprising silicon dioxide. These may include porous silica used as low-k dielectric, which would be utilized in conjunction with a non-porous cap layer comprising TEOS or the like. The scope of the invention should be construed in view of the claims. With this in mind, 

We claim:
 1. A process for manufacturing an integrated circuit wafer comprising: a) providing a silicon wafer with an interconnection metallization pattern thereon having an etch stop layer thereon; b) overlaying said metallization pattern with low K dielectric layer; c) overlaying said low K dielectric with a cap dielectric layer; d) said low K dielectric layer and said cap dielectric layer together comprising an interlevel dielectric layer; e) overlaying said cap dielectric layer with a patterned resist layer defining vias; f) after steps a) through e), installing said silicon wafer in an HDP reactor having adjustable parameters including roof temperature, wall temperature, RF inductive source power, RF bias power, He backside wafer cooler, and means for establishing low pressure, high density plasma therein using fluorocarbon etching gases; g) etching said silicon wafer in said HDP reactor and setting said adjustable parameters to etch completely through said cap layer and said low K dielectric layer while selectively stopping across said entire silicon wafer before etching completely through any portion of said etch stop layer.
 2. The process of claim 1 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns:
 3. The process of claim 1 wherein said low K dielectric is a spin-on dielectric selected from the group consisting of HSQ, SOG, and porous silica.
 4. The process of claim 3 wherein said fluorocarbon etching gases comprise C2F6 and C4F8.
 5. The process of claim 4 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns.
 6. The process of claim 4 wherein said low K dielectric is HSQ.
 7. The process of claim 6 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns.
 8. The process of claim 4 wherein said etch stop layer is selected from the group consisting of Ti, TiN, silicon, silicon nitride, aluminum, aluminum alloy, copper, copper alloy, tantalum, and tantalum alloy.
 9. The process of claim 8 wherein said etch stop layer is selected from the group consisting of Ti, and TiN.
 10. The process of claim 9 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns.
 11. The process of claim 9 further comprising the steps of: adjusting said roof temperature to be within the range 200-240° C.; adjusting said wall temperature to be within the range 200-220° C.; adjusting said RF source power to be within the range 1800-2200 W; adjusting said RF bias power to be within the range 1300-1700 W; adjusting said backside wafer cooler temperature to be within the range −20-0° C.; adjusting said low pressure to be within the range 1-15 mTorr; flowing C4F8 into said HDP reactor at a C4F8 flow rate of 5-10 sccm; flowing C2F6 into said HDP reactor at a C2F6 flow rate of 5-9 sccm; flowing 50-200 sccm Ar gas into said HDP reactor.
 12. The process of claim 11 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns.
 13. The process of claim 12, wherein said HDP etch reactor is an Applied Materials Centura 5300 reactor.
 14. The process of claim 13 wherein: said roof temperature is 230° C.; said wall temperature is 200° C.; said RF source power is 2000 W; said RF bias power is 1500 W; said backside wafer cooler temperature is −10° C.; said low pressure is 4 mTorr; said C4F8 flow rate is 8 sccm; and said C2F6 flow rate is 5 sccm.
 15. The process of claim 14 wherein: said wafer has a diameter of at least 8 inches; said etch stop layer has a thickness not substantially greater than 1100 Angstroms; said interlevel dielectric layer thickness across the entire said silicon wafer is in the range between 0.5 and 2.0 microns; said metallization pattern having a critical dimension of 0.35 microns or smaller; and said defined vias having a diameter less than 0.5 microns.
 16. An integrated circuit intermediate product made by the process of: a) providing a silicon wafer having a diameter of at least 8 inches with an interconnection metallization pattern thereon having an etch stop layer thereon, said etch stop layer having a thickness not substantially greater than 1100 Angstroms, said metallization pattern having a critical dimension of 0.35 microns or smaller; b) overlaying said metallization pattern with low K dielectric layer; c) overlaying said low K dielectric with a cap dielectric layer; d) said low K dielectric layer and said cap dielectric layer together comprising an interlevel dielectric layer, said interlevel dielectric layer having a thickness across the entire said silicon wafer in the range between 0.5 and 2.0 microns; e) overlaying said cap dielectric layer with a patterned resist layer defining vias, said defined vias having a diameter less than 0.5 microns; f) after steps a) through e), installing said silicon wafer in an HDP reactor having adjustable parameters including roof temperature, wall temperature, RF inductive source power, RF bias power, He backside wafer cooler, and means for establishing low pressure, high density plasma therein using fluorocarbon etching gases; and g) etching said silicon wafer in said HDP reactor and setting said adjustable parameters to etch completely through said cap layer and said low K dielectric layer while selectively stopping across said entire silicon wafer before etching completely through any portion of said etch stop layer.
 17. The integrated circuit intermediate product of claim 16, wherein: said fluorocarbon etching gases comprise C2F6 and C4F8; and said low K dielectric is a spin-on dielectric selected from the group consisting of HSQ, SOG, and porous silica.
 18. The integrated circuit intermediate product of claim 17, wherein said low K dielectric is HSQ.
 19. The integrated circuit intermediate product of claim 18, wherein said etch stop layer is selected from the group consisting of Ti and TiN, and wherein said process of making further comprises the steps of: adjusting said roof temperature to be within the range 200-240° C.; adjusting said wall temperature to be within the range 200-220° C.; adjusting said RF source power to be within the range 1800-2200 W; adjusting said RF bias power to be within the range 1300-1700 W; adjusting said backside wafer cooler temperature to be within the range −20-0° C.; adjusting said low pressure to be within the range 1-15 mTorr; flowing C4F8 into said HDP reactor at a C4F8 flow rate of 5-10 sccm; flowing C2F6 into said HDP reactor at a C2F6 flow rate 5-9 sccm; flowing 50-200 sccm Ar gas into said HDP reactor..
 20. The integrated circuit intermediate product of claim 19, wherein: said HDP etch reactor is an Applied Materials Centura 5300 reactor; said roof temperature is 230° C.; said wall temperature is 200° C.; said RF source power is 2000 W; said RF bias power is 1500 W; said backside wafer cooler temperature is −10° C.; said low pressure is 4 mTorr; said C4F8 flow rate is 8 sccm; and said C2F6 flow rate is 5 sccm.
 21. An integrated circuit intermediate product wafer comprising: a) a silicon wafer, said silicon wafer having a diameter of 8 inches or greater, and having active regions patterned therein and having a first metallization layer patterned thereon with a critical dimension of 0.35 microns or smaller, said first metallization layer having an etch stop layer thereon, said etch stop layer having a thickness not substantially greater than 1100 Angstroms; b) a low K dielectric layer atop said etch stop layer; c) a cap dielectric layer atop said low K dielectric layer, said low K dielectric layer and said cap dielectric layer together forming an interlevel dielectric layer, said interlevel dielectric layer having a thickness across the entire said silicon wafer in the range between 0.5 and 2.0 microns; d) high aspect ratio unfilled vias at any diameter value of said wafer, said vias completely opened through both said cap dielectric layer and said low K dielectric layer, said vias having aspect ratio greater than 1, said high aspect ratio vias having a diameter less than 0.5 microns and depths within the range of 0.5 to 2.0 microns across the entire wafer diameter, at least a portion of said etch stop layer remaining across the bottom of substantially all said vias.
 22. The wafer of claim 21 wherein said low K dielectric is selected from the group comprising HSQ, SOG, and porous silica.
 23. The wafer of claim 22 wherein said low K dielectric is HSQ.
 24. The wafer of claim 23 wherein said etch stop layer is Ti or TiN. 